1. Field of the Invention
The present invention relates generally to processes for forming field-effect-transistors within integrated circuits, and more particularly, to a process for forming a field-effect-transistor having a polycide gate structure including a transition metal salicide to reduce sheet resistance of the gate, and having transition metal silicides formed in the source and drain regions to minimize the sheet resistance thereof.
2. Description of the Prior Art
Large scale integrated circuits (LSI) and very large scale integrated circuits (VLSI) often include a large number of field-effect-transistors fabricated upon a single monolithic semiconductor substrate typically formed of single-crystal silicon. Such field-effect transistors are typically formed to have the smallest dimensions permitted by semiconductor processing technology in order to provide as many transistors as possible into a given area on the upper surface of the semiconductor substrate. However, as the physical size of the field-effect-transistors becomes smaller to achieve higher packing densities, the sheet resistances associated with the gate and with the source and drain of each such transistor typically increase. Increased sheet resistance results in decreased signal transmission speeds through the various transistors within the integrated circuit. Consequently, reductions in the sheet resistance associated with the gate and with the source and drain of such field-effect-transistors help increase the signal transmission speed of the integrated circuit.
Another problem which arises from the reduction in the physical size of transistors formed within an integrated circuit is increased contact resistance at the contacts between the gate, source and drain regions of each transistor and the patterned interconnect metalization layer. Interconnecting metalization is typically isolated from the underlying silicon substrate by a glass passivation layer. Contact openings are formed in the insulating glass layer through which the interconnecting metalization makes contact to the gate, source and drain regions of each transistor. As the geometry of each such transistor becomes smaller, the dimensions of such contact openings must also necessarily become smaller. The contact resistance associated with each contact opening is inversely proportional to the contact area. Hence, reduction in the size of such contact openings typically increases the resistance associated with each such contact; higher contact resistance again results in slower signal transmission speeds through the integrated circuit.
Yet another problem encountered in the manufacture of large scale and very large scale integrated circuits is the phenomenon of junction spiking. Spiking occurs when aluminum from the interconnecting metalization layer diffuses into the source or drain silicon regions and penetrates the p-n junction interface between the source or drain diffusion region and the underlying substrate. Such spiking can result in a short circuit between the source or drain contact and the substrate, and produce corresponding circuit failure. Large scale and very large scale integrated circuits require the use of relatively shallow source and drain diffusion regions in order to utilize small device dimensions; accordingly, aluminum atoms may more easily penetrate such shallower junctions to produce a spike at the p-n junction interface.
Two field-effect-transistor integrated circuit processes which are currently used by semiconductor product manufacturers are the polycide gate process using a shallow junction silicide contact, and the polysilicon gate process with salicide. These two processes are described below with reference to FIGS. 7 and 8, respectively.
Prior art FIG. 7 shows the field-effect-transistor structure resulting from the use of the polycide gate process described by Ting in "Silicide For Contacts And Interconnects", IEDM, 1984, pp. 110-113, the disclosure of which is incorporated herein by reference. The isolating field oxide 2 and the thin gate oxide 5 are formed upon the upper surface of the silicon substrate 1 in the conventional manner. A layer of polysilicon 6 is deposited upon the upper surface of substrate 1, followed by the deposition of a layer of a refractory metal silicide such as molybdenum di-silicide (MoSi.sub.2), tungsten di-silicide (WSi.sub.2), tantalum di-silicide (TaSi.sub.2) or titanium di-silicide (TiSi.sub.2). A high temperature cycle for silicide homogenization is then performed to form a composite polycide layer. The polycide layer is patterned by a dry etch process to remove the polycide film except above the gate region of the field-effect-transistor. The formation of polycide in the gate structure reduces the sheet resistance of the gate as compared with the use of polysilicon alone. Source and drain ion implantation and drive-in cycles are then performed in a conventional manner to form source and drain regions 3. Following the deposit of glass passivation layer 4 and formation of contact openings, a transition metal silicide, such as titanium di-silicide (TiSi.sub.2), platinum silicide (PtSi), di-palladium silicide (Pd.sub.2 Si), cobalt di-silicide (CoSi.sub.2) or nickel di-silicide (NiSi.sub.2), may then be deposited through the contact openings to form shallow junction silicide regions (8, 9) to reduce the contact resistance associated with the underlying polycide gate and the underlying silicon source and drain regions. A barrier metal (10), such as titanium tungsten (TiW) or titanium nitride (TiN) is then applied to prevent the subsequent layer of aluminum interconnect metalization (11) from migrating into the silicon source and drain regions (3) and causing junction spiking.
In practice, the above-described polycide gate process achieves some reduction in the gate sheet resistance as compared with a polysilicon gate structure. However, the polycide gate process using shallow junction silicide contacts over the source and drain regions does not significantly reduce the sheet resistance of the source and drain regions.
A field-effect-transistor structure made from the above-mentioned polysilicon gate process with salicide is shown in prior art FIG. 8. This process is also described in the aforementioned technical paper by Ting. The isolating field oxide 2 and thin gate oxide 5 are formed upon the upper surface of substrate 1 in a conventional manner. A layer of polysilicon 6 is deposited upon the upper surface of substrate 1 and is then patterned to form the gate. Source and drain regions 3 are formed by conventional ion implantation and drive-in processes. Oxide side wall spacers (not shown in FIG. 8) are then formed upon the lateral edges of the polysilicon gate, leaving the upper surface of the polysilicon gate and the upper surfaces of the source and drain regions 3 bare. A thin layer of a transition metal, such as Ti, Pt, Co, or Ni, is then deposited on the upper surface of substrate covering the bare source and drain regions 3 and the bare upper surface of polysilicon gate 6. The transition metal layer is then heated to form metal silicides (such as TiSi.sub.2) at both the polysilicon gate and the silicon source and drain diffusion areas. Unreacted transition metal is removed by a selective etch. A passivation layer 4 is applied in a conventional manner, after which contact openings are formed. A barrier metal layer 10 and overlying aluminum-silicon interconnection metal layer 11 are then deposited and patterned in a conventional manner.
The above-described polysilicon gate process with salicide serves to significantly lower the sheet resistance associated with the source and drain regions through formation of a silicide region 8 which extends almost entirely across the source and drain regions 3. The formation of the extensive silicide regions 8 within the source and drain regions additionally reduces the risk of junction spiking. Formation of silicide layer 12 upon the upper surface of polysilicon gate 6 somewhat reduces the sheet resistance associated with the gate, but the resulting gate sheet resistance is still relatively high as compared with the sheet resistance of the above-described polycide gate structure.
Accordingly, it is an object of the present invention to provide a process for forming field-effect-transistors in integrated circuits wherein the sheet resistance associated with the gate of such transistors is relatively low in order to maximize signal transmission speeds.
It is another object of the present invention to provide such a process which can retain the relatively low sheet resistance of the source and drain regions obtained through use of the above-described polysilicon gate process with salicide.
It is still another object of the present invention to provide such a process which achieves lower gate sheet resistances than either the above-described polycide gate process or the above-described polysilicon gate process with salicide.
It is a further object of the present invention to provide such a process which minimizes the occurrence of junction spiking and contact resistance in shallow junction field-effect-transistors.
It is a still further object of the present invention to provide such a process that is compatible with LSI and VLSI fabrication technologies and fabrication apparatus that are commercially available.
It is yet another object of the present invention to provide such a process which is relatively simple and convenient to perform.
It is a further object of the present invention to provide a field-effect-transistor structure resulting from the practice of such a process.